Design of Low Power Reduced Wallace Multiplier with Compact Carry Select Adder, Half Adder & Full Adder Using Cmos Technology

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requires more number of half adder and full adders in the reduction phase. So the chip size (Area) is high in the regular Wallace multiplier. The complexity reduced Wallace multiplier has been designed with less number of half adder and full adders. In this paper, the compact carry select adder, half adder and full adder are designed, which has been incorporated into the complexity reduced Wallace multiplier to reduce the area and delay than the existing reduced Wallace multiplier. The compact half adder and full adder are designed by using static CMOS technology with 6 transistors and 16 transistors instead of 12 transistors and 24 transistors. Also the compact carry select adder has been constructed based on compact half adder with 6 transistors, compact AND, OR and XOR gates with 4 transistors for each gate. So the proposed complexity reduced Wallace multiplier offers low power and less area than the existing Wallace multiplier. Simulation is performed by using Tanner Tool v14.1.